The present invention relates to a double-gated metal oxide semiconductor field effect transistor (MOSFET), and more particularly to a sub-0.05 xcexcm double-gated MOSFET which has excellent short-channel characteristics. The inventive double-gated MOSFET includes a frontside gate electrode comprised of polysilicon and a backside gate electrode that is comprised of an implant region, the two gates are separated by two gate dielectrics and a thin layer of silicon (on the order of about 200 xc3x85 or less) which is sandwiched between the two gate dielectrics. The thin layer of Si serves as the device channel region of the inventive structure. The present invention also relates to a method of fabricating a sub-0.05 xcexcm double-gated MOSFET which employs a dummy gate and a damascene process.
Over the past twenty-five years or so, the primary challenge of VLSI has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly by scaling down MOSFET channel lengths without excessive short-channel effects. Short-channel effects, as is well known to those skilled in the art, are the decrease in threshold voltage, Vt, in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., xe2x80x9cScaling the Si MOSFET: From Bulk to SOI to Bulkxe2x80x9d, IEEE Trans. Elec. Dev., Vol. 39, p. 1074, July 1992 have shown that to reduce short-channel effects in sub-0.05 xcexcm MOSFETs, it is important to have a backside conducting layer to screen the drain field away from the channel. The results published in Yan, et al. show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The main problem associated with the double-gated MOSFET described in Yan. et al. is that the gates have to be fabricated self-aligned to each other and to the source and drain regions. This provides a device with excellent short-channel characteristics, low device capacitance and improved performance. Although Yan, et al. describes the possibility of forming sub-0.05 xcexcm double-gated MOSFET devices, this prior art reference does not disclose a viable and easily manufacturable (which follows conventional CMOS process) means for achieving the same.
In view of the drawbacks associated with prior art double-gated MOSFET technologies, there is a continued need to develop new and improved methods that will permit the successful formation of sub-0.05 xcexcm double-gated MOSFETs, without the need of completely relying on lithography to define the gate regions of the device.
One object of the present invention is to provide a method of fabricating a sub-0.05 xcexcm double-gated MOSFET device with the front and back gates self-aligned to each other and to the source and drain regions.
Another object of the present invention is to provide a method of fabricating a sub-0.05 xcexcm double-gated MOSFET device which has excellent short-channel characteristics.
A further object of the present invention is to provide a method of fabricating a sub-0.05 xcexcm double-gated MOSFET device which includes simple, yet CMOS compatible processing steps.
An even further object of the present invention is to provide a method of fabricating a sub-0.05 xcexcm double-gated MOSFET device which includes a raised source/drain region formed abutting the gate region of the double-gated MOSFET device.
These and other objects and advantages can be achieved by utilizing a method which includes a dummy gate region which is used to define the area for an implanted backside (i.e., bottom) gate electrode as well as defining the channel length of the device and a damascene processing step which is used in forming the frontside (i.e., top) gate electrode of the device. These two gates are separated by two gate dielectrics and a thin (less than about 200 xc3x85) Si layer which is sandwiched between the two gate dielectrics. This thin layer of Si serves as the channel region of the device. Short-channel effects are greatly suppressed in the present invention because the two gates terminate the drain field lines, preventing the drain potential from being felt at the source end of the channel.
In accordance with the present invention, a double-gated MOSFET device is fabricated utilizing the following processing steps:
(a) providing a structure which includes a top wafer bonded to a bottom wafer through a dielectric layer, said top wafer comprising a silicon-on-insulator wafer which includes a buried oxide layer sandwiched between a semiconductor substrate and a semiconducting material layer, wherein said semiconductor material layer is thinner than said semiconductor substrate and is contact with a surface of said dielectric layer, and said bottom wafer comprises a Pxe2x88x92 epi layer formed on a P+ layer;
(b) removing said semiconductor substrate and said buried oxide layer stopping on said semiconducting material layer;
(c) forming a pad oxide layer on said semiconducting material layer;
(d) forming a dummy gate region on a portion of said pad oxide layer, said dummy gate region including a sacrificial region of polysilicon having spacers formed on exposed sidewalls thereof;
(e) forming an oxide layer on other portions of said pad oxide layer that do not contain said dummy gate region, said oxide layer is substantially planar with a top surface of said sacrificial region of polysilicon;
(f) removing said sacrificial region of polysilicon stopping on said pad oxide layer so as to providing an opening;
(g) forming a channel implant region in said semiconducting material layer by implanting though said opening;
(h) forming a backside gate implant region in at least said Pxe2x88x92 epi layer;
(i) removing said pad oxide in said opening and forming a gate dielectric in place thereof;
(j) forming a polysilicon frontside gate region on said gate dielectric in said opening, said polysilicon frontside gate region is substantially planar with said oxide layer; and
(l) removing said oxide layer and said pad oxide layer abutting the spacers.
The dielectric material used in step (a) of the present invention serves as the gate dielectric of the backside gate electrode as well as a diffusion barrier layer.
Following step (l) of the first embodiment of the present invention, it is possible to form raised source/drain regions and/or to carry out conventional back-end-of-the-line (BEOL) processing steps. The raised source/drain regions are formed on the exposed semiconducting material layer that is adjacent to the double-gated MOSFET region.
It is noted that processing steps (a)-(l) mentioned above work well in cases wherein the semiconducting material layer of the SOI wafer has a thickness of about 200 xc3x85 or less. Alternatively, it is possible to utilize a thicker semiconducting material layer, e.g., about 600 xc3x85. When a thicker semiconducting material layer is employed, the inventive method would include repeated oxidation and chemical oxide removal (COR) processes which would be carried out between steps (f) and (g) above, or alternatively between steps (h) and (i) above. The repeated oxidation and COR processing steps are able to thin the semiconducting material layer to ranges that are more desirable for double-gated MOSFET devices.
Another aspect of the present invention relates to a sub-0.05 xcexcm double-gated MOSFET device which has excellent short-channel characteristics. Specifically, the inventive sub-0.05 xcexcm double-gated MOSFET device comprises:
a substrate which includes a source region and a drain region abutting a sub-0.05 xcexcm channel region, said channel region being formed in a semiconducting material layer having a thickness of less than about 200 xc3x85 and being sandwiched between two gate dielectrics;
an implanted backside gate electrode formed beneath said channel region; and
a polysilicon frontside gate electrode formed over said channel region.
The inventive sub-0.05 xcexcm double-gated MOSFET device may also include raised source/drain regions.